The present disclosure relates generally to integrated circuits, and more particularly to a system and method for providing electrostatic discharge (ESD) protection.
Integrated circuits (ICs) may be damaged by ESD phenomena. An IC device may be exposed to ESD generated from many sources such as a human body. Everyday activity such as walking across a floor may cause an accumulation of an electrostatic charge on the body. Simple contact of a fingertip to an IC device allows the body to discharge, possibly causing damage to the IC device. A widely used model used to simulate this event is the Human Body Model (HBM). Obviously, insufficient or improper ESD protection may result in lowering the reliability of the IC and/or may cause permanent damage to the device.
Manufacturers of electrical/electronic devices such as ICs, digital signal processors, radio frequency (RF) circuit devices, printed circuit boards, and other circuits, typically use automatic test equipment (ATE) or similar other test systems to test the devices during the production process, preferably before they are installed by a user. The test systems including an ESD tester are generally configured to apply a test signal to a device under test (DUT) and measure the response.
A technical paper entitled ‘Gate Oxide Failures Due to Anomalous Stress from HBM ESD Testers’, authored by C. Duwury, R. Steinhoff, G. Boselli, V. Reddy, H. Kunz, S. Marum, R. Cline, all of Texas Instruments, Inc., and presented at the Proceedings of EOS/ESD Symposium, pages 132-140, 2004, which is incorporated herein by reference, describes anomalous stress effects from many commercially available HBM ESD testers.
FIG. 1 illustrates a waveform of a typical ESD test signal provided by an ESD tester, according to prior art. An ESD event may be described as a transfer of energy between two bodies having different electrostatic potentials. The transfer may occur through contact or via an ionized discharge such as a spark. The ESD event may be intentional or unintentional. During an ESD event such as performing an ESD stress test, a stress test signal 100 is applied to the DUT such as an IC. A leading pulse 110 (also referred to as a HBM pulse 110 in a HBM model context) represents the intended portion of the ESD stress signal 100. Amplitude IHBM 114 of the HBM pulse 110 may be several amperes, e.g., 1 to 10 amperes, and time duration THBM 112 of the HBM pulse 110 may be approximately 500 nanoseconds (ns). A trailing pulse 120 represents the unintended and often undesirable portion of the ESD stress signal 100. Amplitude ITR 122 of the trailing pulse 120 may be tens of microamperes (μA), with a range up to 1 mA, and time duration TTR 122 of the trailing pulse 110 may be approximately 1 millisecond (ms). A time period TINT 116 between the HBM pulse 110 and the trailing pulse 120 is variable and may depend on the particular characteristics of the ESD tester.
Generally, to avoid damage to the IC during an ESD event, ESD protection devices, e.g., ESD clamps, are typically fabricated on the IC and connected to the IC input/output pads and input/output circuits and other internal nodes of the IC. ESD protection devices generally provide discharge paths so that the internal core circuits of the IC are protected during the ESD event. Damage to the IC device caused by the ESD event is generally determined by the device's ability to dissipate the energy of the discharge and/or withstand the current levels involved therein.
The amplitude of the leading pulse 110 is generally sufficient to trigger ESD clamps on the DUT, thereby protecting the DUT from damage. The amplitude of the trailing pulse 120 is generally low and insufficient to trigger the ESD clamps on the DUT. However, voltage of the IC pad receiving the ESD test signal increases to the breakdown voltage and remains there during the duration TTR 122 of the trailing pulse 120. The high voltage may inject carriers into gate oxide structures of input transistors of the IC causing a threshold shift and/or may cause gate oxide failures. This is undesirable and may cause the DUT to fail the ESD test.
Modifying an ESD tester to eliminate the trailing pulse 120 may be a potential solution. However, this modification may be costly and time consuming. Combined used of modified as well as legacy (unmodified) ESD testers may continue to show inconsistent results and may cause further confusion.
Therefore, a need exists to provide an improved method and system for providing ESD protection to semiconductor devices. Additionally, a need exists to provide an improved technique to cost effectively utilize existing or legacy test system for ESD testing of the DUT. Accordingly, it would be desirable to provide an improved ESD protection system for ICs, absent the disadvantages found in the prior methods discussed above.